By default, it automatically maps key points with the name-first mapping method when it exits the setup mode. It says that p ⇒ q is true when one of these two things happen: (i) when p is false, (ii) otherwise (when p is true) q must be true. .lec file guide the Conformal tool to execute different command in a systematic way. Now, we need to find the actual net connection of this net in the previous LEC pass database. When the comparison is complete, it pinpoints the differences. The key points that the Conformal tool does not map are classified as unmapped points. hbspt.forms.create({ Fig-3 shows the newly added inverter and its input-output connection. While checking, we can easily note that the reported net is connected to one inverter which is missing in the LEC fail database. This paper presents why LEC (Logical Equivalence Check) is important in the ASIC design cycle, how to check it, and what to do when LEC is failing. Let’s take a look at a practical example of LEC failure in a block and see how it can be solved. Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior. Clock gating cells not getting mapped after cloning in revised netlist. Watch how to easily tackle complex and cutting edge designs. For example, if we merge two single bit flops into one multibit flop, it will have D0, D1 as input pins and Q0, Q1 as output pins. A logical equivalence check can be performed between any two representations of a design: RTL vs Netlist or Netlist vs Netlist. Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy. When LEC is failing, the first step is to check the “non-equivalent.rpt” file. The comparison determines if the compared points are: In the case of aborted compare points, we can change the compare effort to a higher setting. In the transition from setup mode to LEC mode, the Conformal tool flattens and models the golden and revised designs and automatically maps the key points. We designate the design types, which are Golden (synthesized netlist) and Revised (generally, the revised design is the modified or post-processed design that the Conformal tool compares to the Golden design). The Conformal tool employs two name-based methods and one no-name method to map key points. At times, the logical connectivity is broken while doing manual fixes or timing ECOs. Conversely, the no-name-mapping method is useful when the Conformal tool must map designs with completely different names. These 152 flip-flops reported as non-equivalent are the multibit flops. Solve your complexity of logical equivalence check in ASIC design cycle, For all career related inquiries, kindly visit our careers page or write to With massively parallel architecture and adaptive proof technology, the Conformal Smart LEC delivers dramatic turnaround time improvements in equivalence checking by over 20X for RTL-to-gate comparisons. Multiple reports are generated once LEC is completed: At the time of sign-off or tapeout phase, the schedule is too tight to handle blocks with some critical logical failure. After finding the reason for the LEC failure, we have to insert one missing inverter and redo the input/output logical connection of this inverter in the LEC failed database. Cadence® Conformal® Logic Equivalence Checking Solutions provide formal equivalence checking of designs from RTL to P&R. Use truth tables to establish these logical equivalences. RTL to GDSII Turnkey ASIC for MEMS Applications. Example 1 for basics. Name-based mapping is useful for gate-to-gate comparisons when minor changes have been made to the logic. Many EDA companies provide tools to do the check. Whereas 152 flops reported in non-equivalent file in LEC fail database are same as fanout of net (BUFT_net_362908) reported in LEC pass database. Now, if we rerun the LEC it will pass and non-equivalent report will show zero non-equivalent points. As it can be seen in Fig-2, once we check this net (BUFT_net_362908) connection in LEC fail database, we see that it is connected only to the input pins of other cell (*_364714/A), but the other connection (driver side) of this net is missing due to unintentional cell deletion. LEC comprises of three steps as shown below: Setup Mode, Mapping Mode and Compare Mode.